High Bandwidth Memory (HBM) HBM1/HBM2/HBM2E/HBM3/HBM4
High Bandwidth Memory (HBM) HBM2/HBM3
- is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM)
- initially from Samsung, AMD and SK Hynix
- the first HBM memory chip was produced by SK Hynix in 2013
- HBM was adopted by JEDEC as an industry standard in October 2013
- HBM2, the second generation, was accepted by JEDEC in January 2016
- HBM3, the third generation, was officially announced by JEDEC on January 27, 2022
HBM - Versions
| Type | Release | Clock (GHz) | Stack | per Stack (1024 bit) | |
|---|---|---|---|---|---|
| Capacity (230 Byte) | Data rate (GByte/s) | ||||
| HBM 1 | Oct 2013 | 0.5 | 8× 128 bit | 1×4 = 4 | 128 |
| HBM 2 | Jan 2016 | 1.0…1.2 | 1×8 = 8 | 256…307 | |
| HBM 2E | Aug 2019 | 1.8 | 2×8 = 16 | 461 | |
| HBM 3 | Oct 2021 | 3.2 | 16× 64 bit | 2×12 = 24 | 819 |
| HBM 4 | 2026 | 5.6 | 2×16 = 32 | 1434 | |
Use Cases
- can be used as VRAM
Resources
, multiple selections available,